Critical External Interrupt and response time
Posted: Fri May 14, 2010 12:40 pm
The system that I have built uses two external interrupts to grab the output of an ADC with a MOD5282.
I have a slow (~1Hz) signal hooked up to Int3 and use a semiphore to detect when this is in the "grab the data" logic state. I then perform an OSSemPend on Int3 (to wait for it return to its "I'm done" state) and enable Int1. During this time, the Int1 ISR grabs the data.
A relatively high speed clock, up to 80 kHz, (an output of the ADC that says when the conversion is complete) is wired to Int1. The Int1 ISR reads in two 16 bit values. The OE (output enable) is used to latch the two 16 bit values from the ADC.
My Int1 ISR is:
INTERRUPT(out_irq1_pin_isr, 0x2700 )
{
sim.eport.epfr = 0x02;/* Clear the interrupt 1 edge 0 0 0 0 0 0 1 0 */
DataBuffer[data_count++] = *ExtLong; //Reads in 2x 16 bit values through D16-D31, A1 toggles.
}
I monitor the delay between the Int1 falling edge (the trigger) and the OE line using a digital scope. This roughly measures the time needed to grab the data. For the most part, the delay is around 5 usec, within my requirement to sample at an 80 kHz sampling rate. However, sometimes the delay as much a 1 msec!!! (Update, > 90 msec!)
Is there anything I can do to prevent this? During the "grab the data" interval, I'd like to disable everything in the MOD5282 except these two interrupts.
Thanks in advance,
Rich
[5-16-10] Further testing shows lag can be >90 msec between Interrupt edge and execution of the ISR. I disabled Autoupdate, DHCP and TCP ports with no sign of improvement. Arggh.
I have a slow (~1Hz) signal hooked up to Int3 and use a semiphore to detect when this is in the "grab the data" logic state. I then perform an OSSemPend on Int3 (to wait for it return to its "I'm done" state) and enable Int1. During this time, the Int1 ISR grabs the data.
A relatively high speed clock, up to 80 kHz, (an output of the ADC that says when the conversion is complete) is wired to Int1. The Int1 ISR reads in two 16 bit values. The OE (output enable) is used to latch the two 16 bit values from the ADC.
My Int1 ISR is:
INTERRUPT(out_irq1_pin_isr, 0x2700 )
{
sim.eport.epfr = 0x02;/* Clear the interrupt 1 edge 0 0 0 0 0 0 1 0 */
DataBuffer[data_count++] = *ExtLong; //Reads in 2x 16 bit values through D16-D31, A1 toggles.
}
I monitor the delay between the Int1 falling edge (the trigger) and the OE line using a digital scope. This roughly measures the time needed to grab the data. For the most part, the delay is around 5 usec, within my requirement to sample at an 80 kHz sampling rate. However, sometimes the delay as much a 1 msec!!! (Update, > 90 msec!)
Is there anything I can do to prevent this? During the "grab the data" interval, I'd like to disable everything in the MOD5282 except these two interrupts.
Thanks in advance,
Rich
[5-16-10] Further testing shows lag can be >90 msec between Interrupt edge and execution of the ISR. I disabled Autoupdate, DHCP and TCP ports with no sign of improvement. Arggh.