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#define PIO_PA6B_PCK0

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arch\cortex-m7\cpu\same70\include\component\pmc.h

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#include <sim.h>
#include <same70.h>
#include <pins.h>
#include <ebi.h>

/* ColdFire chip select base addresses
#define CS1_BASEADDRESS (0xA0000000)
#define CS2_BASEADDRESS (0xB0000000)
#define CS3_BASEADDRESS (0xC0000000)
volatile unsigned short * FPGA_BASE_1;
volatile unsigned short * FPGA_BASE_2;
volatile unsigned short * FPGA_BASE_3;
*/

EBI_CS_cfg_t cs_all_cfg {
	25, // NCS Setup Length in clock cycles
	15, // NRD Setup Length in clock cycles
	25, // NCS Write Setup Length in clock cycles
	15, // NWE Setup Length in clock cycles
	30, // NCS Pulse Length in clock cycles
	65, // NRD Pulse Length in clock cycles
	30, // NCS Write Pulse Length in clock cycles
	65, // NWE Pulse Length in clock cycles
	90, // NRD Cycle Length
	90, // NWE Cycle Length
	0,  // TDF Cycle Count (clock cycles to release data reqd. by ext. device; can be 0-15)
	EBI_BUS_WIDTH_16,
	EBI_BYTE_ACCESS_SELECT,
	EBI_NWAIT_DISABLED,
	EBI_WRITE_MODE_NCS,
	EBI_READ_MODE_NCS
};

extern volatile uint8_t ebi_2_base[];  // Chip select 2
extern volatile uint8_t ebi_0_base[];  // Chip select 0
extern volatile uint8_t ebi_3_base[];  // Chip select 3

void InitChipBoardSelect() {
	/* ColdFire enable/configure chip selects.
	sim.cs[1].csar = (CS1_BASEADDRESS >> 16);
	sim.cs[1].cscr = 0x2180;                     // 0010 0001 1000  0000
	sim.cs[1].csmr = 0x03FF0001;

	sim.cs[2].csar = (CS2_BASEADDRESS >> 16);
	sim.cs[2].cscr = 0x2180;                     // 0010 0001 1000  0000
	sim.cs[2].csmr = 0x03FF0001;

	sim.cs[3].csar = (CS3_BASEADDRESS >> 16);
	sim.cs[3].cscr = 0x2180;                     // 0010 0001 1000  0000
	sim.cs[3].csmr = 0x03FF0001;
	
	FPGA_BASE_1 = (unsigned short *) CS1_BASEADDRESS;
   	FPGA_BASE_2 = (unsigned short *) CS2_BASEADDRESS;
	FPGA_BASE_3 = (unsigned short *) CS3_BASEADDRESS;
	*/

	// Note: EBI #CS1 is not available to the user - reserved for chip select of the MODM7AE70 SDRAM (U2)
	P1[5].function(PINP1_5_NCS2); // FPGA #CS1
	P1[6].function(PINP1_6_NCS0); // FPGA #CS2
	P1[7].function(PINP1_7_NCS3); // FPGA #CS3
	P1[8].function(PINP1_8_NRD);

	ConfigureEBI_CS(2,cs_all_cfg); // FPGA #CS1
	ConfigureEBI_CS(0,cs_all_cfg); // FPGA #CS2
	ConfigureEBI_CS(3,cs_all_cfg); // FPGA #CS3

	EnableExtBusBuff(true); // Enable the on-module bus buffers

	/**** Route Master Clock to Programmable Clock 0 (P1[31])
	  Control peripheral clock 0 via Power Management Controller structure.
	  PMC->PMC_SCSR = System Clock Status Register (31.20.3)
	  PMC->PMC_PCER0 = Peripheral Clock Enable Register 0
	  PMC->PMC_PCDR0 = Peripheral Clock Disable Register 0
	  PMC->PMC_PCSR0 = Peripheral Clock Status Register 0
	  PMC->PMC_PCK[7] = Programmable Clock 0 Register (31.20.13)
	 ****/
	P1[31].function(PINP1_31_PCK0); // Configure P1[31] with the Peripheral B: Programmable Clock 0 Output
	
	PMC->PMC_WPMR = PMC_WPMR_WPKEY(PMC_WPMR_WPKEY_PASSWD) | 0; // Disable PMC write protect for all clock config operations.
	PMC->PMC_SCDR |= PMC_SCDR_PCK0; // Disable Programmable Clock 0
	PMC->PMC_PCK[0] = PMC_PCK_PRES(0) | PMC_PCK_CSS(PMC_PCK_CSS_MCK); // Set PMC_PCK[0] to master clock with prescalar 0.
	PMC->PMC_SCER |= PMC_SCER_PCK0; // Enable Programmable Clock 0
}