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INTERRUPT( PwmModule3ValueMatch_ISR, 0x2700 )
{
sim1.mcpwm.sm[3].sr |= PWM_MATCH_VAL3_INT_ENABLE;
IsrTick = !IsrTick;
SetStatusLed(STATUSLED2, IsrTick);
sim2.edma.tcd[30].csr &= 0xFF7F;
sim2.edma.tcd[30].csr |= 0x0001;
sim2.edma.tcd[31].csr &= 0xFF7F;
sim2.edma.tcd[31].csr |= 0x0001;
}

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#define FB_CS1_BASE	0x01000000;			// CS_1 base address
#define AD1reading	*(DWORD*) FB_CS1_BASE
#define FB_CS4_BASE	0x04000000;			// CS_4 base address
#define AD2reading	*(DWORD*) FB_CS4_BASE

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void InitCS (void)
{
sim1.gpio.par_cs |= _00111100_;		// activate CS1 & CS4 pin function (primary function for those pins)
sim2.cs[1].csar = FB_CS1_BASE;		// set base address for CS1
sim2.cs[1].cscr = 0x00000500;			// 1 wait state, internal transfer acknowledge, 32 bit transfer
sim2.cs[1].csmr = 0x00000101;			// CS1 range = FB_CS1_BASE...FB_CS1_BASE+0xFFFF, read only + valid
sim2.cs[4].csar = FB_CS4_BASE;		// set base address for CS4
sim2.cs[4].cscr = 0x00000500;			// 1 wait state, internal transfer acknowledge, 32 bit transfer
sim2.cs[4].csmr = 0x00000101;			// CS4 range = FB_CS4_BASE...FB_CS4_BASE+0xFFFF, read only + valid
}

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void InitPWM_DMA (void)
{
// general/common eDMA control register setup
sim1.gpio.par_cs |= _00111100_;	// J1-5 => CS1 function (FIFO RAM 1 OE), J1-6 => CS4 function (FIFO RAM 2 OE)
sim2.edma.cr 	  &= ~0x000300FF;	// Leave the group priorities alone, but clear all other control flags (default eDMA setup)
sim2.edma.erql	  |=  0xC0000000;

// transfer control description block for transfer from CIS1 Sample FIFO RAM to normal RAM
volatile edma_tcdstruct &tmrTcd1 = sim2.edma.tcd[30]; // eDMA channel 30: software triggered, see Table 19-6 in MCF54418RM_V3.PDF
tmrTcd1.saddr  	= FB_CS1_BASE;								// set the start address for the DMA transfer
tmrTcd1.attr   	= 0x0202;									// no address modulo's, source/target both 32 bit (4 bytes)
tmrTcd1.soff   	= 0; 											// source offset: this must be 0, the source address is always the same !
tmrTcd1.nbytes 	= SAMPLES_PER_CIS*4;						// number of bytes transferred per DMA request (samples x 4 bytes/sample)
tmrTcd1.slast  	= 0; 											// source offset applied at completion of all requests, before resetting
tmrTcd1.daddr  	= (DWORD)g_ulRawSampleDataCIS1;		// Raw pixel data address
tmrTcd1.doff   	= 4; 											// destination offset, how much to move destination address after each request
tmrTcd1.dlast_sga = -(SAMPLES_PER_CIS*4);					// destination address adjustment at the end of the major loop (bytes).
tmrTcd1.biter		= 1;											// major loop count reload value (single DMA transfer per request)
tmrTcd1.citer		= 1;											// initial loop count value (single DMA transfer per request)
tmrTcd1.csr    	= 0; 											// default DMA operations, no interrupts, leave request enabled when DMA ends

// transfer control description block for transfer from CIS4 Sample FIFO RAM to normal RAM
volatile edma_tcdstruct &tmrTcd2 = sim2.edma.tcd[31]; // eDMA channel 31: software triggered, see Table 19-6 in MCF54418RM_V3.PDF
tmrTcd2.saddr  	= FB_CS4_BASE;								// set the start address for the DMA transfer
tmrTcd2.attr   	= 0x0202;									// no address modulo's, source/target both 32 bit (4 bytes)
tmrTcd2.soff   	= 0; 											// source offset: this must be 0, the source address is always the same !
tmrTcd2.nbytes 	= SAMPLES_PER_CIS*4;						// number of bytes transferred per DMA request (samples x 4 bytes/sample)
tmrTcd2.slast  	= 0; 											// source offset applied at completion of all requests, before resetting
tmrTcd2.daddr  	= (DWORD)g_ulRawSampleDataCIS2;		// Raw pixel data address
tmrTcd2.doff   	= 4; 											// destination offset, how much to move destination address after each request
tmrTcd2.dlast_sga = -(SAMPLES_PER_CIS*4);					// destination address adjustment at the end of the major loop (bytes).
tmrTcd2.biter		= 1;											// major loop count reload value (single DMA transfer per request)
tmrTcd2.citer		= 1;											// initial loop count value (single DMA transfer per request)
tmrTcd2.csr    	= 0; 											// default DMA operations, no interrupts, leave request enabled when DMA ends
}

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INTERRUPT( PwmModule3ValueMatch_ISR, 0x2700 )
{
DWORD test;
sim1.mcpwm.sm[3].sr |= PWM_MATCH_VAL3_INT_ENABLE;
IsrTick = !IsrTick;
SetStatusLed(STATUSLED2, IsrTick);
test = AD1reading;
test += AD2reading;
test+=1;
//sim2.edma.tcd[30].csr &= 0xFF7F;
//sim2.edma.tcd[30].csr |= 0x0001;
//sim2.edma.tcd[31].csr &= 0xFF7F;
//sim2.edma.tcd[31].csr |= 0x0001;
}

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#define FB_CS1_BASE	0x02000000;			// CS_1 base address
#define AD1reading	*(DWORD*) FB_CS1_BASE
#define FB_CS4_BASE	0x02010000;			// CS_4 base address
#define AD2reading	*(DWORD*) FB_CS4_BASE