NetBurner Community Forum

I have a 480x272 Sony PSP TFT LCD.

I saw a schematic where a guy took a TFT much like this one and wired it directly to the uP. i am assumuing he set up an interrupt to fire @ 9MHZ rate for the PCLK, and Hsync, Vsync and is updating the pixel data much like a graphics controller would. For thoes of you who are way more familuar with these MOD motorola processors, would doing somthing like this be to labor intensive to do ?

Giving you a real answer would probably take more time than I can spare at the moment, but I think I can give you more of the right questions to get you going in the right direction.

Getting the processor involved at the individual pixel-writing level would probably impose too much load to work right. Almost certainly so if you tried to do an interrupt for each dot (I haven't checked, but it's very unlikely that the Coldfire can handle 9 million interrupts per second).

But what might well work with the MOD5270 would be to use a DMA channel to write the data from the frame buffer to the LCD. The big question is whether you could, say, use one of the on-chip timers to pace the DMA to the right speed to keep the LCD happy. When people do this kind of design, they often wind up picking the CPU clock speed to match it to what the display needs. This would mean that the CPU would only have to do one interrupt per horizontal scan line. In fact, depending on the timing requirements, you might even be able to set up the entire frame as one DMA operation (probably not, but LCDs don't have the physical retrace time requirements that CRTs do, so it's at least a possibility). The interrupt routine doesn't have that much to do, so, if you can make sure that it's the top system priority, it should be possible to keep both the LCD and the rest of the system happy.

Hope this helps.

Ran

The DMA idea sounds like it is on the right track. The DMA timer can directly trigger the DMA to transfer so this would be used to pace the writes. To really capture the power of the DMA you will want to transfer data from the SRAM. The SRAM is dual ported so it is possible for the processor and the DMA to access this memory simultaneously. This must be enabled in the RAMBAR register. If you had DMA pulling data from SDRAM addresses then the bus would be tied up and the processor will be stalled.

lgitlitz wrote:The DMA idea sounds like it is on the right track. The DMA timer can directly trigger the DMA to transfer so this would be used to pace the writes. To really capture the power of the DMA you will want to transfer data from the SRAM. The SRAM is dual ported so it is possible for the processor and the DMA to access this memory simultaneously. This must be enabled in the RAMBAR register. If you had DMA pulling data from SDRAM addresses then the bus would be tied up and the processor will be stalled.

A correction on that.... When you write to the LCD the SDRAM will be blocked no matter what since the external bus will be in use. If you are pulling the data from SRAM then at least you only stall the bus during the writing of data and not from the reading too.

-Larry

Thanks Guys, I suppose there is nothing wrong with giving it a try.
Just trying to keep parts count low, and not to load the system to much in the process.