NetBurner Community Forum

I've got a custom FPGA blade designed for the PK70 that mostly works, but for some goofiness that I cannot figure out. I believe the problem likely lies in the interface between the data bus of the PK70 and the FPGA. My suspicion is that I need to add constraints in the Xilinx tools to get the timing right, but I'm not sure how to do that.

FWIW - we didn't go with the Netburner NBPKX500, because at the time we started this project, it didn't exist! I'm probably going to use that in the future. Anyway, it occurred to me that, if that module was designed to support implementing an interface with the data bus, maybe an example exists that could help me.

So, is the FPGA connected to the data bus in that blade, and does anyone have an example of implementing such an interface? This has been a problem for quite some time, so I would really appreciate any help.

Thanks!

That blade stores the FPGA config in the PK70 program then downloads it into the FPGA then after that talks to the FPGA via the data bus.

So the pins were preselected to be the configuration pins...

If you installed the PK70 tools fro0m the latest builds you should already have all that code...
nburn\examples\pk70\xilinxblade....

Both the interface code and the verilog code on the other side....

If you have space then I highly recommend that you add some read/write test registers to your FPGA so you can verify the interface.

The Schematic for that blade is attached...

Paul

It was many years ago that I interfaced an FPGA to a NetBurner. I was relatively new to FGPA design then, but do remember that I needed to add wait states to on the NetBurner side. I don't believe that you should have to do that since the FPGA should easily be able to handle the ColdFire timing. In my case, I'm sure that it was poor FPGA design on my part. In a future product I interfaced a NetBurner to a CPLD (that I didn't design) and had no issues with the interface nor did I need to add wait states.

To make a long story short, you will need to add timing constraints to the FPGA design to ensure a proper design. Not a trivial task.

bb

pbreed wrote:That blade stores the FPGA config in the PK70 program then downloads it into the FPGA then after that talks to the FPGA via the data bus.

So the pins were preselected to be the configuration pins...

If you installed the PK70 tools fro0m the latest builds you should already have all that code...
nburn\examples\pk70\xilinxblade....

Both the interface code and the verilog code on the other side....

If you have space then I highly recommend that you add some read/write test registers to your FPGA so you can verify the interface.

The Schematic for that blade is attached...

Paul

Hi Paul,

Sorry for the long delay. Your response helped, as it validated my hardware design. I added some constraints, but that didn't fix the issue. Finally, I found the bug in my VHDL, even though I was convinced the problem wasn't there! As usual, never be too sure of anything...

Thanks for the help,
Bob