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I have to read 2 encoders with my 5282, and was wondering if i could use a hctl-2022, this counter uses an 8 bit interface so i could plug it into the data bus on j1 right?

FYI

the LS7366 quad decoder is a lot cheaper and has a 4-wire serial interface. Mouser and Digikey don't carry it, you buy directly from LSI. 1.98 each I think I remember

Chris

was looking at that one but we order all our stuff from digikey...

If the encoders aren't "too" fast I've done this with the 4 edge port bits available. Mine was for a couple manual adjuster knobs so never bothered to calc. or meas. max throughput.

Speed is an issue looking into using a couple of lcxr2245's and the 7760do, just trying to narrow down the clock source... and am i right on thinking i can use the j1 data bus pins for this?

Yes

use a 7hc02 to qualify the chip select and the read/write signals, use a 'hc244 buffer between the chip and the databus that is selected by the '02 parts

with the 7760 parts you don't need the '244 or the '02 parts, you use the QSPI to talk to the 7760 parts along with two QSPI chip select signals

Chris

Chris Ruff wrote:Yes

use a 7hc02 to qualify the chip select and the read/write signals, use a 'hc244 buffer between the chip and the databus that is selected by the '02 parts

with the 7760 parts you don't need the '244 or the '02 parts, you use the QSPI to talk to the 7760 parts along with two QSPI chip select signals

Chris

7366 is spi, 7760 is parallel, since i'm only using one 7760 was going to ground the chip select, instead of a hc244 using 2x lcxr2245 buffer for chip select / rw / address & buffer

having problems finding documentation on interfacing and using the databus, anyone have any info?

Thanks

I am not sure what '7760' is.

The HCTL2022 has a buffer at the tail end. You will not need the '244 buffer. It appears that the CS1* signal from NB would go to one of the select lines on the 2022 (possibly invert) and the R/W* signal from NB would go to oe* signal on 2022. The DB top 8 bits from NB would go to 2022 data bits.

You will need to check all of this- especially the CS1* to SEL1. And probably tie SEL2 hi or lo.
I didn't study the data sheet enough to be sure.

Generally speaking, one can never tie any chip select to the active state (unless there is more than one). Be careful there.

Chris

The DB interface code will look something like below:

Study the freescale data sheet to learn more about page size, wait states, etc. that are all set here by
non-obvious hex numbers

you call InitCS1 only once at program start

//
//
#define CHIPLOC 0x30000000
//
// set up CS1 for external memory
//
// **||*************************************************************
char InitCS1()
// **||*************************************************************
{
// base address
sim.cs[1].csar = (CHIPLOC >> 16);
// WS A 32
// |2ws|0A PS
sim.cs[1].cscr = 0x1d80; /* 0000 1101 1000 0000 */
// bit 0 == 1 means all above is valid....
sim.cs[1].csmr = 0x00ff0001; // the ff is the block size
return 0;
}

#define CHIPADDR1 (0x30000000)

void WriteSumpin(short val)
{
volatile unsigned short *pBase1 = ( volatile unsigned short * ) CAHIPADDR1;
*pFlashBase1 = val;
}

short ReadSumpin()
{
volatile unsigned short *pBase1 = ( volatile unsigned short * ) CAHIPADDR1;
short val = *pBase1;
return val;
}

Chris