The problem being I only have the address lines A0-A15 coming out of the module and the SDRAM has A0-A16. However could I use two chip selects and a bit of LV logic to create an A16 signal for my SDRAM chip


ie A16 = CS1
CS = CS1 & CS2
The problem is CS1 and CS2 are asseted after the address bus is setup by the CPU for rd/wr access. So will my pseudo A16 signal be setup to late for SDRAM access to work?